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We looked inside some of the posts by richardwhitesell-blog and here's what we found interesting.
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The successful tapeout of ASIC chips requires the DRC rules to be met for the better DFM yields. By using the methods explained in this paper, the different DRC violations related to the technology node 7nm can be addressed.
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Delivering a lower technology node design project on time is important in today’s dynamic and competitive market. However, there are many unknowns at lower geometry which impacts on project/product scheduled delivery.
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MBIST is a self-testing and repair mechanism which tests the memories through an effective set of algorithms to detect possibly all the faults that could be present inside a typical memory cell whether it is stuck-at (SAF), transition delay faults (TDF), coupling (CF) or neighborhood pattern sensitive faults (NPSF). It uses an inbuilt clock, address and data generators and also read/write controller logic, to generate the test patterns for the test.
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Antenna violations can be fixed by adding a diode for increasing the gate area, or by applying layer hopping for reducing metal area. For boundary net’s antenna violation, there is always a dependency on the next full chip signoff cycle, because at the block level these cannot be verified after applying local fixes.
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ASIC design flow is a mature and silicon-proven IC design process which includes various steps like design conceptualization, chip optimization, logical/physical implementation, and design validation and verification. Let’s have an overview of each of the steps involved in the process.
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MBD is used effectively, it provides a single design platform to optimize overall system design. It helps embedded software developers to understand the difference between simulator and software development tool in order to create simulation models and check whether algorithms will work before the embedded code is written.
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DFM saves on time; cost and effort related to product redesigning process and carves out best-manufacturing output efficiently. It takes care of factors which might impact product manufacturing including the nature of raw material, its physical and chemical attributes and its availability for faster production.
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In a SystemVerilog test bench, it often happens that multiple drivers would try to drive a single net or output of gate. In this scenario, the output value is best determined based on the signal driving strength of each driver and its corresponding value.
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During SoC verification, you must view the design at the top level and extract its SoC level functionality/features during specification study phase for its verification. At this stage, a thorough understanding of SoC functionality and its architecture is required because misunderstanding of the specification can become the leading cause of bugs, and due to this, you may waste unnecessary time on issues which are not real RTL problems.
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Reducing the body thickness results into lower mobility as surface roughness scattering increases. Since FinFET is a 3-D structure, it is less efficient in terms of thermal dissipation. Also, if we scale down the FinFET transistor size further, say below 7nm, the leakage issue becomes dominant again.
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Physical design (is also known as integrated circuit layout) is a process in which the front end design transfer the structural netlist to the back end design team to convert into a physical layout database which consists of geometrical design information for all the physical layers which is used for interconnections.
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With the increase in the adoption of various embedded applications, smartphones, and connected devices, Qualcomm has launched multiple variants of its Snapdragon platforms such as 625, 660 and 835 to address diverse compute and performance needs across different verticals. Cost-effectiveness and high-quality features are the goals of these Qualcomm Snapdragon platforms.
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Product engineering service can be defined as an engineering consulting activity, which uses various hardware, embedded, software and IT services solution for the designing and development of products.
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2.5D and 3D are the best alternatives to transistor scaling in order to sustain Moore’s law and can achieve better throughput with an optimized area, performance and cost. It is most suitable for high-performance ASICs like HMCs (Hybrid Memory Cube), NAND flash, Optical sensors and Networking ASICs.
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The successful tapeout of ASIC chips requires the DRC rules to be met for the better DFM yields. By using the methods explained in this paper, the different DRC violations related to the technology node 7nm can be addressed.
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There seem to be quite a few problems associated with RISC-V verification, out of which the most significant ones will be explained in this blog along with the primary advantages that formal verification offers.
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DFT is becoming a key factor that saves higher design cost, higher power consumption, increasing execution testing time, chip area, pin counts, and other new fault types at small geometries in the testing phase itself.
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