#8 bit embedded microcontrollers software

[jhhn2yalls]

https://www.futureelectronics.com/p/semiconductors--microcontrollers--8-bit/atmega128l-8au-microchip-2038197

What is 8 bit microcontroller, lcd microcontrollers, low power microcontrollers

ATmega Series 128 KB Flash 4 KB SRAM 8 MHz 8-Bit Microcontroller - TQFP-64

[dgls2nett]

https://www.futureelectronics.com/p/semiconductors--microcontrollers--8-bit/pic18f4520-i-pt-microchip-3154588

low power 8 bit microcontrollers, lcd microcontrollers, Microcontroller software

PIC18F Series 32 KB Flash 1.5 kB RAM 40 MHz 8-Bit Microcontroller - TQFP-44

[athur2llmm]

https://www.futureelectronics.com/p/semiconductors--microcontrollers--8-bit/ez80f91az050ek-zilog-8131964

Embedded microcontroller, microcontroller board, lcd microcontrollers

eZ80F91 Series 256 kB Flash 8 kB RAM 50 MHz 8-Bit Microcontroller - LQFP-144

[grhm2illo]

https://www.futureelectronics.com/p/semiconductors--microcontrollers--8-bit/pic16lf877a-i-ml-microchip-5373501

Embedded microcontrollers, microcontroller programming, USB microcontroller

PIC16 Series 14 kB Flash 368 B RAM 20 MHz 8-Bit Microcontroller - QFN-44

[shrm2lph]

https://www.futureelectronics.com/p/semiconductors--microcontrollers--8-bit/atmega128l-8au-microchip-2038197

lcd microcontrollers, Low power microcontroller, microcontroller software

ATmega Series 128 KB Flash 4 KB SRAM 8 MHz 8-Bit Microcontroller - TQFP-64

[ryy2gton]

https://www.futureelectronics.com/p/semiconductors--microcontrollers--8-bit/pic18f6520-i-pt-microchip-7337520

8-bit microprocessor, 8 bit embedded microcontroller, Low power microcontroller

PIC18F Series 32 kB Flash 2 kB RAM 40 MHz 8-Bit Microcontroller - TQFP-64

[tmslsburr]

https://www.futureelectronics.com/p/semiconductors--microcontrollers--8-bit/pic16c73b-04-sp-microchip-1274299

Microcontrollers, 8 bit, PIC16C73B-04/SP, Microchip

PIC16 Series 192 B RAM 4 K x 14 Bit EPROM 8-Bit CMOS Microcontroller - SPDIP-28

[rndy2prkr]

https://www.futureelectronics.com/p/semiconductors--microcontrollers--8-bit/pic16c73b-04i-so-microchip-9673831

lcd microcontrollers, Microcontrollers software, Wireless microcontroller

PIC16 Series 192 B RAM 4 K x 14 Bit EPROM 8-Bit CMOS Microcontroller - SPDIP-28

[vict2leelso]

https://www.futureelectronics.com/p/semiconductors--microcontrollers--8-bit/pic16c73b-20i-so-microchip-8276131

8 bit Embedded microcontrollers, 8 bit Wireless microcontrollers, programming

PIC16 Series 192 B RAM 4 K x 14 Bit EPROM 8-Bit CMOS Microcontroller - SPDIP-28

[nicla2llard]

Pic microcontroller, Programmable lcd microcontrollers, embedded microcontroller

PIC16F Series 1.75 kB Flash 224 B RAM 20 MHz 8-Bit Microcontroller - SOIC-18

[mrng2ches]

Microcontroller manufacturers, Wireless microcontrollers

PIC16 Series 14 KB Flash 512 B RAM 32 MHz 8-Bit Microcontroller - TQFP-44

[thdor2wnn]

What is a 8 bit microcontroller, lcd microcontroller, low power microcontroller

PIC18F Series 32 kB Flash 2 kB RAM 40 MHz 8-Bit Microcontroller - TQFP-64

[grhm2illo]

https://www.futureelectronics.com/p/semiconductors--microcontrollers--8-bit/pic16lf877a-i-ml-microchip-5373501

Embedded microcontrollers, microcontroller programming, USB microcontroller

PIC16 Series 14 kB Flash 368 B RAM 20 MHz 8-Bit Microcontroller - QFN-44

[govindhtech]

Intel Quartus Prime Pro Edition 25.1 Optimized for Agilex 3

Altera Launches Quartus Prime Pro Edition 25.1 for Agilex 3 FPGAs

Now available is Quartus Prime Pro 25.1, which supports Agilex 3, the latest Agilex release. Developers may design high-performing, power-efficient edge and embedded programs with this update.

Comprehensive Agilex 3 FPGA support

Agilex 3 FPGA family offers cost optimisation, high performance, and power efficiency for edge and embedded applications. This version lets you develop, test, and implement solutions faster with Agilex 3 higher-speed transceivers, on-chip dual Cortex-A55 ARM CPUs, and increased memory support, including LPDDR4.

For small board space applications, Agilex 3 uses Intel's variable pitch BGA packaging to design more efficiently and compactly. With this technology, developers can maintain performance and power efficiency while adding functionality to smaller spaces.

Security is essential for FPGA applications to protect sensitive data and IP. Agilex 3's physical security, authentication, and encryption capabilities strengthen designs' manipulation and assault resistance.

Nios V Soft Processor Enhancements

Nios V is vital for embedded applications and improves efficiency and performance. These improvements allow developers to make smaller, more efficient embedded devices.

Improved Nios V/g Core Performance Improved work completion and overall performance.

Nios V/c Core Area reduction saves 8% space, leading in smaller designs.

The Ashling RISCFree IDE's Visual Studio Code plugin simplifies Nios V software development.

TinyML Example Design with Nios V Application Note lets developers add machine learning (ML) to FPGA designs utilising microcontrollers.

Features of Embed Software

FPGA-based embedded applications need strong OS and virtualisation support. By adding Linux, RTOS, and hypervisor support, Quartus Prime Pro 25.1 lets developers build scalable, real-time, and virtualised embedded systems.

Linux Hardware Reference Designs Regular and standard editions for Linux development.

To support Xen, developers can virtualise FPGA programs.

RTOS supports Zephyr and Bare Metal, and FreeRTOS will arrive in Q2 (May).

Installer Improvements: Faster, flexible configuration

FPGA software should install and adapt easily. Quartus Prime Pro 25.1 improves installation with parallel processing, configurable component selection, and file management.

Installation in Parallel speeds up setup by installing many components simultaneously.

By letting users choose just the bits they need, Dynamic Components decrease installation time and disc space.

Troubleshoot hardware quickly with streaming debugging

Effective debugging reduces development cycles. The Streaming Debug IP for Signal Tap helps engineers debug FPGA designs by capturing real-time, high-bandwidth data.

Hardware debugging streaming allows real-time data flow for analysis.

Configurable streaming via STP Signal Tap Logic Analyser configures streaming and selects a debug host.

Simulation Enhancements

Quartus Prime Pro 25.1 improves integration, long-term support, and simulation with new native Altera AXI4 Bus Functional Models (BFMs).

Optimised for Quartus simulation workflows, native Altera AXI4 BFMs increase performance and compatibility.

Smooth Change With better toolchain integration, customers may switch to Altera AXI4 BFMs without substantial modifications.

Quartus Prime Pro 25.1 improves simulation performance, notably for transceiver protocol IP, enabling faster debugging and verification.

Better Transceiver Protocol IP simulation enhances PCIe, Ethernet, Serial Lite, JESD, and other transceiver protocols.

25.1 Beta Models The new simulation models for this edition focus on Ethernet and PCIe and are under beta testing.

Improved Efficiency Usually, 50% or more improvements speed up verification and reduce simulation time.

These simulation additions improve Quartus Prime Pro 25.1's transceiver-based FPGA design capabilities by speeding up simulations and reducing verification time.

Extra Quartus Prime Pro 25.1 Updates

QPDS Standard & Pro Containerised Images Docker Hub offers Quartus Prime Standard and Pro Editions containerised, simplifying deployment and improving cloud and CI/CD compatibility.

Separating timed closure data from Design Assistant results simplifies failure classification in Summary of Design Closure.

SDC Relative File Paths improve portability and script management for Synopsys Design Constraints (SDC) reports.

MTBF improvements It lets users adjust instance toggling rates to improve MTBF when default toggle rates are not suitable.

Static timing analysis improvements in Quartus Prime Pro 25.1 speed up timing problem identification and resolution.

Synthesis supports basic Quad-Port RAM. Automatic quad-port RAM inference expands memory design flexibility.

Complete Support for Byte Enable Inference in Synthesis: This adds 8-bit byte enables and supports 5, 8, 9, and 10-bit combinations, matching hardware capabilities.

Correcter Management Users can now write individual bytes within a word using the byte enable control signal to increase memory access and performance.

Better RAM inference lets designers use FPGA memory more readily.

FPGA AI Suite: Improved Usability and AI

As AI advances, FPGA-based inference systems must be more flexible and effective. This release includes better performance estimation, model support, and Agilex FPGA integration.

Support Agilex 3 Beta FPGA AI Suite beta supports Agilex 3 FPGAs. Build in Quartus with Agilex 3 and generate Inference IP targeting Agilex 5 in the architectural configuration file.

The RPM and DEB packages are now called “altera-fpga-ai-suite-” and the AI Suite is installed in “/opt/altera” instead of “/opt/intel”.

YoloV7 Model Support enables high-accuracy object recognition in robotics, surveillance, and industrial quality control.

Agilex 5 FPGA E-Series Example Design Support New Agilex 5 FPGA E-Series 065B Modular Development Kit sample designs are available.

This SoC example uses an ARM host CPU for AI inference. AI Inference IP and a novel layout transform enable folding and run-time configurability to improve AI model performance and usability.

Example of Hostless JTAG-Attach Design A system console linked to the Inference IP via JTAG allows users to setup and control IP functionality step-by-step.

Performance Estimator Uses Memory Bandwidth Users may now define external memory bandwidth when designing for memory-limited devices like Agilex 5 and Agilex 3, improving accuracy.

OpenVINO 2024.6 Integration FPGA AI Suite 25.1 uses the latest OpenVINO 2024.6 for stability and maintainability.

For two years, Quartus Prime Pro versions will only include the Long-Term Support AI Suite, which uses new optimisations and performance improvements.

FPGA AI Suite 25.1 simplifies FPGA AI inference with faster performance, more example designs, and greater model support.

Quartus Prime Pro 25.1 IP Features

After adding Agilex 3 IP cores and upgrading Agilex 5, Quartus Prime Pro 25.1 delivers real-time data processing, flexible memory access, and rapid connectivity for many applications.

Agilex 3 IPs

Agilex 3 has a wide range of memory, processor, and connectivity IPs for low-cost applications:

1.25 Gbps LVDS and MIPI D-PHY high-voltage and fast adaptable I/O Assistance interfaces.

PCIe 3.0, 10GE Hard IP, and 12.5Gbps transceivers ensure high-bandwidth applications.

LPDDR4 provides cost-effective embedded memory up to 2133 Mbps.

HPS EMIF ensures tight ARM Cortex integration.

HD Image and Video Processing Our VVP package accelerates video and vision processing applications.

JESD204B for Synchronising Data Converters synchronises 12.5Gbps multi-channels accurately.

The Transceiver Toolkit for Advanced Debugging improved transceiver link testing and debugging.

Agilex 5 IP updates

Performance and flexibility enhancements to Agilex 5 series IP include:

PMA-Direct real-time adaptive reconfiguration of multiple configurations

PCIe 3.0/4.0 Multi-Channel DMA supports x2/x4 Root Port (RP) and Endpoint (EP) modes.

Agilex 5 D Series enabled 12.5 Gbps per serial channel in Interlaken for scalable data transport.

Transceiver Toolkit 17.16 Gbps JESD204B Advanced Debugging ensures rapid, accurate data flow.

Dual-Simplex Mode Protocol JESD204C expands high-speed ADC/DAC interface for more advanced signal processing.

O-RAN IP: Supports 15–240 KHz subcarrier frequencies and real-time spacing changes via control messages. Scalable and conserved digital power.

The Agilex 3 and Agilex 5 FPGAs are ideal for embedded, networking, and AI-driven applications due to their performance, efficiency, and adaptability.

Conclusion

Quartus Prime Pro 25.1 improves Agilex 3 support, debugging tools, AI acceleration, IP cores, and usability. Optimisation for embedded apps, high-speed interfaces, or AI workloads is faster, more efficient, and more flexible with this version.

[atoquarks]

[lanshengic]

Microchip launches MPLAB® Machine Learning Development Kit to help developers easily integrate machine learning into MCUs and MPUs

【Lansheng Technology News】Microchip Technology Inc. recently launched a new MPLAB® machine learning development toolkit, providing a complete integrated workflow to simplify machine learning model development. Available across Microchip's broad portfolio of microcontrollers (MCUs) and microprocessors (MPUs), this software toolkit enables developers to quickly and efficiently add machine learning inference.

Rodger Richey, vice president of Microchip's Development Systems Business Unit, said: "Machine learning is the new normal for embedded controllers. Leveraging machine learning at the edge can make products more efficient, more secure, and less power-intensive than systems that rely on cloud communications for processing. Lower. Designed specifically for embedded engineers, Microchip’s unique integrated solutions are the first to support not only 32-bit MCUs and MPUs, but also 8-bit and 16-bit devices, enabling efficient product development.”

Machine learning works by using a set of algorithms to analyze and generate patterns from large data sets to support decision-making. Machine learning is generally faster, easier to update, and more accurate than human processing. Microchip customers can leverage this new set of tools to enable predictive maintenance solutions to accurately predict potential problems with equipment used in a variety of industrial, manufacturing, consumer and automotive applications.

MPLAB Machine Learning Development Kit helps engineers build efficient, small-footprint machine learning models. Powered by AutoML, the toolkit eliminates many repetitive, tedious, and time-consuming model building tasks, including extraction, training, validation, and testing. It also provides model optimization capabilities to meet the memory constraints of MCUs and MPUs.

When used in conjunction with the MPLAB X integrated development environment (IDE), the new toolkit provides a complete solution. It can be easily implemented by people with almost no knowledge of machine learning programming, saving the cost of hiring data scientists. It also has advanced features that meet the needs of experienced machine learning designers.

Microchip also offers the option to extract models from TensorFlow Lite and use them in any MPLAB Harmony v3 project. MPLAB Harmony v3 is a fully integrated embedded software development framework that provides flexible, interoperable software modules to simplify the development of value-added functions and shorten product time to market. Additionally, the VectorBlox™ Accelerator Software Development Kit (SDK) provides the most energy-efficient artificial intelligence/machine learning (AI/ML) inference capabilities based on convolutional neural networks (CNN) using PolarFire® FPGAs.

The MPLAB Machine Learning Development Kit provides the necessary tools to design and optimize edge products that run machine learning inference. Visit the Microchip Machine Learning Solutions page to learn more about streamlining your development process, reducing costs and accelerating time to market with Microchip’s intuitive machine learning tools.

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