#Dynamic RAM

[techav]

Wrap030-ATX Remembers

No general-purpose computer will do much without a good amount of Random Access Memory for transient storage of code and data. Now that I have confirmed basic operation of CPU, bus controller, ROM, and serial, it's time to turn my attention to main system memory.

Every homebrew computer I've built to date, including previous iterations of the Wrap030 project, has used Static RAM. Static RAM is nearly as simple as peripherals can be — give it an address, assert a Chip Enable and a Read or Write strobe signal, wait a bit, and release. Done, cycle complete. If you don't need to retrieve some data for a good long while, it's no matter so long as the chip still has power. For a small system, SRAM is reliable and dead simple to use.

The problem with SRAM is it is also very expensive. The 2MB of SRAM I had on the previous iteration of Wrap030 cost over $20 — and it's still far from enough to run an operating system like Unix System V, NetBSD, Linux, etc. This is the reason computers generally use Dynamic RAM for primary system memory.

The difference is SRAM uses several transistors to create a flip-flop for storing each and every bit of memory, whereas DRAM uses a capacitor to store each bit of memory. This reduces manufacturing costs and increases storage density, but does come with some trade-offs. Most notably, the capacitors that store bits in DRAM will lose their charge — and the stored data with it — after a rather brief period of time. This means the DRAM capacitors need to be topped off regularly in a process known as a refresh cycle.

Another complication of using DRAM is the bus interface has been changed to allow much larger storage capacities without the physical chip package growing to absurd sizes. Instead of the chip accepting the entire address at once, it expects to be given a Row address (along with a Row Address Strobe [RAS#]) then a Column address (along with a Column Address Strobe [CAS#]), with myriad specific timing requirements for when each signal should be asserted and deasserted.

In short, DRAM is much more difficult to interface with compared to SRAM, so I've never really gotten around to it.

With one of the long term goals of this project being running a *nix operating system though, I'm going to need the larger memory that DRAM affords. So i made provision for a CPLD to serve as a dedicated DRAM controller on the Wrap030-ATX motherboard and added a couple 72-pin SIMM slots. In theory this setup should be able to support up to 256MB of RAM (if rare 128MB SIMMs should fall into my hands...).

So where do we turn when dealing with complicated timing with multiple modes and a bunch of I/O? Why, Finite State Machines, of course! That bit where the DRAM expects a row address for a little while, that's a state. And the following bit where the DRAM expects a column address is another state. And then another state to make sure the DRAM has enough time to write or fetch the data. The round it out with one last state to tell the CPU data is ready.

What about that weird refresh timing? Well, that's just few more states for the state machine. And then one last "idle" state that waits for a refresh timing counter to hit 0 or for the CPU to start a bus cycle. Laid out like that, the DRAM controller became a state machine with 7 or 8 states, a counter, and an address multiplexer.

The logic actually came together easier than expected. Not completely without bugs of course.

There's this note in the datasheets about startup initialization where the DRAM should not be accessed 200μs after power on, and there should be 8 refresh cycles before the first access. Initially I had built this entire sequence into my logic. It consumed a ton of resources and didn't really work right.

I realized that my reset circuit held the CPU in reset for longer than 200μs on power on, so I was guaranteed that first initialization time. So I removed that startup delay from my DRAM controller logic, and made a few tweaks to the state machine so it could do 8 back-to-back refresh cycles after reset.

I was able to successfully write to DRAM and read that data back!

That much proved to be the easy part. The next steps were confirming DRAM accesses worked reliably, that I had the order of my byte select signals correct, that I could identify the amount of installed memory, and that all of the installed memory was working. These are programming problems, not logic problems, and I am not a strong programmer. On top of that, not only am I working with unproven DRAM logic, but I'm also using untested SIMMs that I had picked up from Computer Reset.

I quickly ran into errors, but was it a problem with my logic? A problem with my timing? A problem with the SIMMs?

I had a large back of 72-pin SIMMs, split fairly evenly between Fast Page Mode (FPM) and Extended Data Output (EDO) types. I tried them all. Some would pass the tests for nearly all addresses but fail at the end. Some seemed to have a stuck bit. Some were just plain bad and gave errors everywhere. It didn't really answer the question about whether my logic was bad, but results were consistent enough for me to think that maybe the logic might be ok.

And then finally I came across a pair of HP-branded 8MB EDO SIMMs that passed a simple write-read test without error ...

... right around the time my serial port stopped working. But the memory test was passing, and I could at least see the serial output on the logic analyzer.

The serial port problem was a bit setback. It had been working but suddenly wasn't. Clearly the UART itself was working, I just wasn't getting anything past the level shifter. Well that at least gave me a starting point of where to look. Sure enough, one of the 12V supply pins was not well soldered. Thankfully a quick fix.

Back to testing memory, I started writing a program to identify the size of the installed SIMM and write a register I added to the DRAM controller to configure the specific geometry of the installed memory. See, DRAM has another lovely quirk — chips of the same size may have a different configuration of Row and Column sizes. For instance one chip may have a 9-bit Column and a 10-bit Row, but the next may have a 10-bit Column and a 9-bit Row, and both are the same size. If the DRAM controller just assumes 12-bit Row and Column (the largest supported by 72-pin SIMMs), then there will be gaps in the memory map that will need to be accounted for in software (using MMU, for example). If the DRAM controller knows the geometry of the installed memory, then it can present the memory to the CPU as one contiguous block of memory.

And that's where I found my next bug. The system would just hang when trying to write to that DRAM controller configuration register.

... because I had forgotten to complete that part of the state machine. The result was the state machine would end up in a state for writing to the configuration register, but then it couldn't get out of it. Once I added the missing condition to the state machine logic I was able to correctly identify the geometry and size for my installed memory!

Wow that was long. This has been the biggest, most involved step in the process of bringing up this computer yet. It turns out there are a lot of moving pieces that have to all work together to get the computer running code from ROM and reading/writing DRAM.

Now that I have my main memory working, I should be able to get some software running. I'm hoping to at least have BASIC running in time for VCFSW at the end of June.

[kyfite]

It's time to rip and tear in some jolly cooperation

[shyjusticewarrior]

[sidsinning]

Mylene in “Derision”: “Having bad mom doesn’t excuse your behaviour”

Felix in “Emotion”: “uwu I committed a world genocide because I had a bad dad”

Me: ???

I will say Felix is a lot more complex and sympathetic in his circumstances, bc the harm he causes LB and Paris is in service to those he cares about- his fellow sentibeings. He believes he is doing something GOOD (ofc still enjoying sweet revenge against Bad Adults™ - which they are so, fair LOL), while everything Chloe sets out to do is to make herself feel good with absolutely no benefit to anybody- and she fully understands that.

I will give Felix props for apologizing to Kagami and Adrien after Mari seemingly disappears forever because of him at least

I guess the only "solace" the show wants us to be satisfied with is their own actions biting them in the ass in the end but

eh

(Mari deserves like 100000x apologizes from you Felix like holy shit you made her have a panic attack and worse)

(Also sidenote rewatching Emotion Felix's entire plot was heavy as hell, I feel like they fumbled the bag with him going from breaking down in tears from having to kill one of his own kind that he made himself, to making him Kagami's boyfriend the very next ep he appears??? idk focus became wack besides his weird theater kid backstory scene after🥴🥴🥴)

[suuho]

감사합니다 / THE AUDITORS (2024) dir. Kwon Young-il, Joo Sang-gyu

[liquidstar]

it must have been so confusing tutoring subaru from a lugnican perspective, like, how the hell do you invent an entire syllabary all on your own and still be completely fucking illiterate

[monkiinart]

not tagging this bc theres a shippy in here but. furry lady gang

[eowyntheavenger]

Truly nobody is doing it like them

[mx-mongoose]

“Max would be friends with Kurt and Ram”

Okay, I would agree with this but the more I think about it, I don’t think he would? Max is a lot of things and yes he does beat up people and has a God complex. But I think he would draw the line at being friends with rapists and would beat the shit out of them. My points being-

- A: He’s into Grace and tries to flirt with her with sexual comments, yes, and he’s an asshole for that. But he never physically forces himself onto her and tries to woo her into getting with him. He sees Grace as more of a challenge and does genuinely respect her in his own way.

- B: The jocks/friends he surrounds himself with aren’t sexist and are good people who just get pushed around by him. They pick on Grace and call her ugly because she’s a nerdy prude like all the other victims they pick on.

- C: I genuinely think he would view Kurt and Ram as weak desperate bitches that have to force themselves onto somebody because no-one wants them

- D: Hatchetfield as a whole is very accepting towards the queer community to the point where the people who really shouldn’t be supportive, like the Chastitys, will still use your pronouns even though they think you’re going to hell. So if Kurt and Ram try to bully a kid for being queer, Max would view it as them just trying to pick a low hanging fruit because, damn it, his bullying is a damn art form and he’s not just gonna go for an easy low blow.

So yeah, I think Max would be buddy buddy with them at first until he finds out who they actually are and then beats them up behind a dumpster.

[osamudadzai]

i wanna write this fy/osig fanfiction. really super bad. i have an idea in my head. but i'm so. bad at writing fyodor but i don't know anyone personally who understands him really well and i wouldn't willingly show this to people because it's .. kind of a lot

[shyjusticewarrior]

Catwoman and Poison Ivy

Selina and Ivy's friendship is so underrated. Selina was so important to Ivy's character development.

Their friendship really developed in Gotham City Sirens 2009, when Ivy was really defined by her trust issues.

Selina theoretically should be the last person Ivy should trust but proved otherwise over and over again.

In Ram V's Catwoman run, Selina not only figuratively but literally protected the kind and idealistic side of Ivy.

[aznack]

When Enot smells/hears survivor cooking something, they will go up and try to flirt to try to get Survivor to give them some of the food, Survivor almost always relents as soon as possible but gets back at them later by flirting back when they're done eating.

[ultravioart]

Okay but why are artists tagging ships on fanart on tumblr (thank you for doing so, it allows me to filter things that trigger, as tagging systems SHOULD work) but then those artists post that same art untagged on Twitter???? So I can't filter it with blacklisting words???

It's causing me to freaking backcheck EVERY fanart of Ram and Zen on Twitter now, ruins any enjoyment when I have to worry the art I am looking at is ship art of family dynamics. I just want to enjoy platonic Shambali bros.

:( please tag your ships on both Twitter and Tumblr, etc... It's not fair to fans within fandoms that you draw stuff with a ship intent but then post it untagged. Especially for niche characters. And it doesn't matter what fandom or what ship. Tagging a main character tag but not the ship makes fandom spaces less accessible. And not just so people can avoid the content--you would get more eyes on your creations if you tagged properly! So what gives?

I personally always aim to tag my ships, as well as state when I intend something to be platonic. Making people have to double check between your accounts is really bad fandom etiquette. ,:/

And yeah... not going to apologize for asking people to tag ships (regardless of what the ship is) because I have OCD and I am on the spectrum, so avoiding needless instances of triggers is apart of me taking care if my mental health, and being able to access sfw content of my sfw special interests shouldn't be controversial to ask for... Tagging makes the internet more accessible for a wide variety of people, so PLEASE tag ships.

[horngryeyes]

dvattra: ❌ dva doesnt deserve nice things

ramjourn: ✅ i love both of them

[stuck-in-the-ghost-zone]

first time writing the greats i need 2 do them the correct amount of justice or else ill explode and die

[ride-thedragon]

I think my next Nettles analysis is my most deranged yet.

I'll do it in a cute way. It's just a lot of imagery for such a minor character, I feel insane.